FEX-Emu's engineering blog exposes a brutal truth: translating x86 instructions to ARM is the easy part. The real problem is memory ordering. X86 enforces Total Store Ordering, giving software strong guarantees about when writes become visible across CPUs. ARM uses a weaker model that permits aggressive reordering for efficiency. Bridging that gap naively, by wrapping every memory operation in ARM acquire/release instructions, is expensive enough to kill performance.
The article catalogs specific failure modes with hard numbers. Unaligned accesses that x86 handles silently require FEX to catch faults and dynamically patch translated code with barriers. Split-lock operations can run hundreds to thousands of times slower than the normal case, requiring kernel excursions and signal handlers. Write-combined GPU memory is the worst offender: FEX measured bandwidth degradation exceeding 800x in the worst case, dropping some games below 1 FPS. Mitigations exist but are piecemeal. Apple added a hardware TSO mode to Apple Silicon. Qualcomm's Oryon cores support coherent cache-line atomics. Valve shipped a Linux kernel patch targeting specific unaligned atomic cases.
Read the full post for the technical depth, not just the conclusions. The breakdown of how each ARM extension partially addresses each x86 assumption, and where the gaps remain, is the actual value here. It reframes emulation as an archaeology problem: recovering four decades of undocumented behavioral contracts that x86 software silently depends upon.
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