Cisco exceeded its $1 billion AI revenue target for FY25, ended August, with guidance pointing higher next year. Will Eatherton, who leads Cisco networking engineering for hyperscale and datacenter, sat down with SemiAnalysis to explain how a company that missed the early cloud era is now competing directly against Arista, Broadcom, and NVIDIA-backed Mellanox in GPU interconnect infrastructure. The revenue was driven by GPU-to-GPU backend networking using fixed and modular chassis switches, not legacy enterprise product lines.
The technical argument is worth reading in full. Cisco is converging around 512 to 1,000 port radix targets using both higher-rate ASICs and modular systems, the same trajectory as NVIDIA and Broadcom. On software, Cisco claims to be the third-largest contributor to SONiC after Microsoft and NVIDIA, and is actively building modular chassis support into the open-source OS. The P200, their latest Silicon One chip, is brought up simultaneously on IOS-XR, NX-OS, and SONiC on day one. That multi-stack approach is a direct reversal of the proprietary lock-in strategy that defined Cisco for two decades.
The piece also covers wide-area DCI architecture for multi-datacenter GPU workloads, where Eatherton argues IOS-XR and segment routing give Cisco an edge that pure leaf-spine vendors cannot match. The NVIDIA partnership, which Eatherton says was not easy to negotiate, is the near-term wedge into customers who would not have considered Cisco for AI infrastructure two years ago. If you follow AI networking supply chains, the SONiC contributor data and the modular chassis discussion are the sections to read.
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