Nvidia's Rubin CPX delivers 20 PFLOPS of FP4 dense compute with only 2TB/s of memory bandwidth and 128GB of GDDR7, a deliberate tradeoff that makes it purpose-built for the prefill phase of LLM inference. Prefill is compute-bound, not memory-bound, so strapping it to expensive HBM with 20.5TB/s of bandwidth, as found on the dual-die R200, is wasteful. The CPX solves that waste directly.
This announcement expands the VR200 family into three rack configurations: the baseline VR200 NVL144 with 72 R200 GPU packages, the VR200 NVL144 CPX mixing 72 R200 packages with 144 CPX packages across 18 trays, and the Vera Rubin CPX Dual Rack pairing a full VR200 NVL144 rack with a dedicated 144-CPX rack. Every competitor, AMD included, now has to plan a prefill-specific chip in addition to catching up on rack-scale design, a problem they have not yet solved since the GB200 NVL72 Oberon announcement in March 2024.
The full piece is worth reading for its breakdown of how disaggregated serving, splitting prefill and decode across specialized hardware, only reaches its efficiency ceiling when both phases have matched silicon. The competitive analysis of AMD and custom ASIC providers is specific and unsparing, and the rack configuration comparison gives you the exact unit counts to understand what Nvidia is actually selling to hyperscalers.
[READ ORIGINAL →]